高效数字递归类除法算法的实现

N. Neelima, Aruru Sai Kumar, A. Jayanth, K. K. Mahitha, A. Dilip, K. Reddy
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引用次数: 0

摘要

电子系统的基本要素是算术运算。算术运算是任何电子应用程序的组成部分,而算法是用于进行计算或解决问题的一系列指令。尽管加法、减法、乘法和除法是电子系统中算术实现的基本组成部分,但除法的实现受到的关注远远少于其他算术运算的实现。用这种方法除两个数的过程,除了得到一个余数外,还得到一个商。事业部业务的实施极具挑战性;因此,在这种情况下,采用复杂的方法来确保成功实现。要想取得成功,系统必须在分割电路中具有稳定的性能。在本工作中,使用Verilog HDL编程语言开发了数据大小为8位、16位和32位的无符号整数的恢复除法和非恢复除法算法,它们属于数字递归类的范畴。这些算法分别适用于数据值为8、16和32位的无符号整数。在每一种算法中,计算都在三个寄存器中的一个中进行,寄存器由字母A、Q或M指定。
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Implementation of Efficient Digit Recurrence Class of Division Algorithms
The basic elements of an electronic system are arithmetic operations. Arithmetic operations are the building block of any electronic application and algorithm is a sequence of instructions used to carry out calculations or solve problems. In spite of the fact that addition, subtraction, multiplication, and division are fundamental components of arithmetic implementation in the electronic system, the implementation of division has received far less attention than the implementation of the other arithmetic operations. The process of dividing two numbers using the method results in the production of a quotient in addition to a remainder. The implementation of division operations is highly challenging; thus, in this scenario, a complex method is employed to ensure successful implementation. To be successful, a system has to have a solid performance in the division circuit. In this body of work, the Restoring division and Non-restoring division algorithms, which fall under the category of Digit Recurrence Class, have been developed for unsigned integers with data sizes of 8 bit, 16 bit, and 32 bit using the Verilog HDL programming language. These algorithms are applicable to unsigned integers with data values of 8, 16, and 32 bits respectively. In each of these algorithms, the calculation takes place in one of three registers designated by the letters A, Q, or M.
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