C. Calligaro, A. Manstretta, A. Modelli, G. Torelli
{"title":"多层快闪记忆体的技术与设计限制","authors":"C. Calligaro, A. Manstretta, A. Modelli, G. Torelli","doi":"10.1109/ICECS.1996.584556","DOIUrl":null,"url":null,"abstract":"This paper discusses basic constraints for multilevel storage in flash memories. Aspects such as programming algorithms, threshold voltage distribution, data retention, read disturbs, sense amplifier sensitivity and cell transconductance spread are considered. Experimental results and design considerations are provided. Guidelines for the evaluation of multilevel storage feasibility are given. The feasibility of four-level storage with present technologies using a read voltage around 6 V is demonstrated.","PeriodicalId":402369,"journal":{"name":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"40","resultStr":"{\"title\":\"Technological and design constraints for multilevel flash memories\",\"authors\":\"C. Calligaro, A. Manstretta, A. Modelli, G. Torelli\",\"doi\":\"10.1109/ICECS.1996.584556\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses basic constraints for multilevel storage in flash memories. Aspects such as programming algorithms, threshold voltage distribution, data retention, read disturbs, sense amplifier sensitivity and cell transconductance spread are considered. Experimental results and design considerations are provided. Guidelines for the evaluation of multilevel storage feasibility are given. The feasibility of four-level storage with present technologies using a read voltage around 6 V is demonstrated.\",\"PeriodicalId\":402369,\"journal\":{\"name\":\"Proceedings of Third International Conference on Electronics, Circuits, and Systems\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"40\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Third International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.1996.584556\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Third International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.1996.584556","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Technological and design constraints for multilevel flash memories
This paper discusses basic constraints for multilevel storage in flash memories. Aspects such as programming algorithms, threshold voltage distribution, data retention, read disturbs, sense amplifier sensitivity and cell transconductance spread are considered. Experimental results and design considerations are provided. Guidelines for the evaluation of multilevel storage feasibility are given. The feasibility of four-level storage with present technologies using a read voltage around 6 V is demonstrated.
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