Kohki Taniguchi, N. Miura, Taisuke Hayashi, M. Nagata
{"title":"专用自适应电源谐振抑制","authors":"Kohki Taniguchi, N. Miura, Taisuke Hayashi, M. Nagata","doi":"10.1109/VTS.2015.7116273","DOIUrl":null,"url":null,"abstract":"This paper presents an adaptive supply-resonance (SR) suppression scheme at a product testing stage. Dedicated to each product in different assembly forms, an on-chip power-delivery-network analyzer identifies SR frequency and autotunes notch filter for SR noise suppression. The feasibility has been silicon-proven by a prototype demonstration in 0.18μm CMOS successfully.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"93 Pt A 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"At-Product-Test Dedicated Adaptive supply-resonance suppression\",\"authors\":\"Kohki Taniguchi, N. Miura, Taisuke Hayashi, M. Nagata\",\"doi\":\"10.1109/VTS.2015.7116273\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an adaptive supply-resonance (SR) suppression scheme at a product testing stage. Dedicated to each product in different assembly forms, an on-chip power-delivery-network analyzer identifies SR frequency and autotunes notch filter for SR noise suppression. The feasibility has been silicon-proven by a prototype demonstration in 0.18μm CMOS successfully.\",\"PeriodicalId\":187545,\"journal\":{\"name\":\"2015 IEEE 33rd VLSI Test Symposium (VTS)\",\"volume\":\"93 Pt A 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 33rd VLSI Test Symposium (VTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2015.7116273\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 33rd VLSI Test Symposium (VTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2015.7116273","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents an adaptive supply-resonance (SR) suppression scheme at a product testing stage. Dedicated to each product in different assembly forms, an on-chip power-delivery-network analyzer identifies SR frequency and autotunes notch filter for SR noise suppression. The feasibility has been silicon-proven by a prototype demonstration in 0.18μm CMOS successfully.