{"title":"按覆盖监测BIST","authors":"M. Gossel, H. Jurgensen","doi":"10.1109/EURDAC.1993.410639","DOIUrl":null,"url":null,"abstract":"The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the signature analyzer. Because of a large number of don't-care conditions for the cover circuits the hardware overhead is very low. All faults in the fault model under consideration are detected either by the cover circuits or, due to an erroneous signature, by the signature analyzer.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Monitoring BIST by covers\",\"authors\":\"M. Gossel, H. Jurgensen\",\"doi\":\"10.1109/EURDAC.1993.410639\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the signature analyzer. Because of a large number of don't-care conditions for the cover circuits the hardware overhead is very low. All faults in the fault model under consideration are detected either by the cover circuits or, due to an erroneous signature, by the signature analyzer.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410639\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410639","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

作者展示了如何将传统的内置自检方法与一种简单的组合电路在线错误检测方法相结合。在测试模式下,由一盖和零盖组成的错误检测电路监测特征分析仪的一个或多个组件的输出序列。覆盖电路只需要检测被信号分析器掩盖的故障。由于覆盖电路有大量的不关心条件,所以硬件开销很低。所考虑的故障模型中的所有故障都可以由覆盖电路检测到,或者由于错误的签名而由签名分析仪检测到。
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Monitoring BIST by covers
The authors show how to combine a conventional built-in self-test method with a simple method for online error detection for combinational circuits. The output sequence of one or more components of the signature analyzer is monitored, in test mode, by an error detection circuit consisting of a one-cover and a zero-cover. The cover circuits need to detect only such faults that are masked by the signature analyzer. Because of a large number of don't-care conditions for the cover circuits the hardware overhead is very low. All faults in the fault model under consideration are detected either by the cover circuits or, due to an erroneous signature, by the signature analyzer.<>
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