具有回拷和160mb /s突发传输特性的二级缓存芯片的结构与设计

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111122

K. Uchiyama, H. Aoki, O. Nishii, S. Hatano, O. Nagashima, K. Ooishi, J. Kitano

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引用次数: 6

摘要

介绍了一种二级缓存芯片的结构和设计，该芯片支持多级缓存之间的高速(160 mb /s)突发传输和一种新提出的缓存一致性协议。该芯片包括32kb的数据存储器、42kb的标签存储器和21.7 K-gate逻辑，并支持50mhz的CPU。给出了性能和设计结果

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Architecture and design of a second-level cache chip with copy-back and 160 MB/s burst-transfer features

The authors describe the architecture and design of a second-level cache chip which supports high-speed (160-Mb/s) burst transfer between multilevel caches and a newly proposed cache-consistency protocol. This chip includes a 32-kB data memory as well as a 42-kb tag memory and 21.7 K-gate logic, and it supports a 50-MHz CPU. Performance and design results are presented

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Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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