{"title":"基于纳米机电开关的三元内容可寻址存储器","authors":"Manhee Cho, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332924","DOIUrl":null,"url":null,"abstract":"Content Addressable Memory (CAM) is a type of memory that searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. In this paper, we propose static based architecture for low-power high-speed Ternary CAM (TCAM), using Nanoelectromechanical (NEM) Memory Switch for nonvolatile data storage. We build 10-bits TCAM word array based on NEM Memory Switch with benefit of low power consumption and low chip density. We design the proposed TCAM architecture on commercial 65-nm process with 1.2 V operating voltage.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory\",\"authors\":\"Manhee Cho, Youngmin Kim\",\"doi\":\"10.1109/ISOCC50952.2020.9332924\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Content Addressable Memory (CAM) is a type of memory that searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. In this paper, we propose static based architecture for low-power high-speed Ternary CAM (TCAM), using Nanoelectromechanical (NEM) Memory Switch for nonvolatile data storage. We build 10-bits TCAM word array based on NEM Memory Switch with benefit of low power consumption and low chip density. We design the proposed TCAM architecture on commercial 65-nm process with 1.2 V operating voltage.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9332924\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9332924","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory
Content Addressable Memory (CAM) is a type of memory that searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. In this paper, we propose static based architecture for low-power high-speed Ternary CAM (TCAM), using Nanoelectromechanical (NEM) Memory Switch for nonvolatile data storage. We build 10-bits TCAM word array based on NEM Memory Switch with benefit of low power consumption and low chip density. We design the proposed TCAM architecture on commercial 65-nm process with 1.2 V operating voltage.