R. Khamankar, B. Jiang, R. Tsu, W. Hsu, J. Nulman, S. Summerfelt, M. Anthony, J. Lee
{"title":"一种用于ULSI DRAM的高介电常数BST薄膜的新型低温工艺","authors":"R. Khamankar, B. Jiang, R. Tsu, W. Hsu, J. Nulman, S. Summerfelt, M. Anthony, J. Lee","doi":"10.1109/VLSIT.1995.520890","DOIUrl":null,"url":null,"abstract":"BST (BaSrTiO/sub 3/) thin films are being widely studied as alternative dielectrics for ULSI DRAM storage capacitors. An important issue involved in the use of these films is related to the process integration with silicon technology. For example the high temperatures at which the films are typically deposited and/or annealed is one of the major concerns. In this paper we demonstrate, for the first time, a new technology whereby high quality BaSrTiO/sub 3/ films are obtained at a temperature as low as 460/spl deg/C without any post deposition anneals. Excellent resistance to electrical stress and post-deposition processing steps are also demonstrated.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A novel low-temperature process for high dielectric constant BST thin films for ULSI DRAM applications\",\"authors\":\"R. Khamankar, B. Jiang, R. Tsu, W. Hsu, J. Nulman, S. Summerfelt, M. Anthony, J. Lee\",\"doi\":\"10.1109/VLSIT.1995.520890\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"BST (BaSrTiO/sub 3/) thin films are being widely studied as alternative dielectrics for ULSI DRAM storage capacitors. An important issue involved in the use of these films is related to the process integration with silicon technology. For example the high temperatures at which the films are typically deposited and/or annealed is one of the major concerns. In this paper we demonstrate, for the first time, a new technology whereby high quality BaSrTiO/sub 3/ films are obtained at a temperature as low as 460/spl deg/C without any post deposition anneals. Excellent resistance to electrical stress and post-deposition processing steps are also demonstrated.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"66 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520890\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520890","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel low-temperature process for high dielectric constant BST thin films for ULSI DRAM applications
BST (BaSrTiO/sub 3/) thin films are being widely studied as alternative dielectrics for ULSI DRAM storage capacitors. An important issue involved in the use of these films is related to the process integration with silicon technology. For example the high temperatures at which the films are typically deposited and/or annealed is one of the major concerns. In this paper we demonstrate, for the first time, a new technology whereby high quality BaSrTiO/sub 3/ films are obtained at a temperature as low as 460/spl deg/C without any post deposition anneals. Excellent resistance to electrical stress and post-deposition processing steps are also demonstrated.