M. Sekine, S. Ueda, M. Kogure, T. Takei, Masami Aihara, E. Yano, K. Iwawaki, K. Yamagishi, K. Kohno, T. Kitahara, T. Fukasawa
{"title":"先进的设计系统:设计捕获、功能测试生成、混合电平仿真和逻辑综合[VLSI]","authors":"M. Sekine, S. Ueda, M. Kogure, T. Takei, Masami Aihara, E. Yano, K. Iwawaki, K. Yamagishi, K. Kohno, T. Kitahara, T. Fukasawa","doi":"10.1109/CICC.1989.56789","DOIUrl":null,"url":null,"abstract":"A VLSI CAD (computer-aided design) system has been enhanced by adding several tools. It consists of a mixed-level simulator, logic synthesis, layout systems, a functional test generation assistance, etc. The functional simulator, which is on a laptop PC, is for a 50 K-gate class LSI, and the mixed level simulator, which is on an EWS and a mainframe, is for above-100 K-gate VLSI. In-house designer groups have reported that the design time is cut in half using the system. A functional schematic capture provides a more friendly user interface than a logic schematic capture. A novel approach to functional test generation is also provided","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"An advanced design system: design capture, functional test generation, mixed level simulation and logic synthesis [VLSI]\",\"authors\":\"M. Sekine, S. Ueda, M. Kogure, T. Takei, Masami Aihara, E. Yano, K. Iwawaki, K. Yamagishi, K. Kohno, T. Kitahara, T. Fukasawa\",\"doi\":\"10.1109/CICC.1989.56789\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A VLSI CAD (computer-aided design) system has been enhanced by adding several tools. It consists of a mixed-level simulator, logic synthesis, layout systems, a functional test generation assistance, etc. The functional simulator, which is on a laptop PC, is for a 50 K-gate class LSI, and the mixed level simulator, which is on an EWS and a mainframe, is for above-100 K-gate VLSI. In-house designer groups have reported that the design time is cut in half using the system. A functional schematic capture provides a more friendly user interface than a logic schematic capture. A novel approach to functional test generation is also provided\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56789\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56789","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An advanced design system: design capture, functional test generation, mixed level simulation and logic synthesis [VLSI]
A VLSI CAD (computer-aided design) system has been enhanced by adding several tools. It consists of a mixed-level simulator, logic synthesis, layout systems, a functional test generation assistance, etc. The functional simulator, which is on a laptop PC, is for a 50 K-gate class LSI, and the mixed level simulator, which is on an EWS and a mainframe, is for above-100 K-gate VLSI. In-house designer groups have reported that the design time is cut in half using the system. A functional schematic capture provides a more friendly user interface than a logic schematic capture. A novel approach to functional test generation is also provided