双电平LVDS技术,使数据传输线减少LCD驱动IC的一半

Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho
{"title":"双电平LVDS技术,使数据传输线减少LCD驱动IC的一半","authors":"Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho","doi":"10.1109/ESSCIR.2004.1356682","DOIUrl":null,"url":null,"abstract":"A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC\",\"authors\":\"Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho\",\"doi\":\"10.1109/ESSCIR.2004.1356682\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"81 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356682\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356682","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

提出了一种双低压差分信号(DLVDS)电路,旨在减少LCD驱动IC的传输线数量。在该电路中,我们将一对原始数据应用于DLVDS电路作为输入。输入作为互补信号。然后,发射器将两个输入转换为两种完全差分电平信号。因此,只需要两条传输线来传输两个原始输入,同时保持LVDS特性。接收机通过电平解码电路恢复原始输入数据。我们采用0.25 /spl mu/m CMOS技术设计了所提出的电路。因此,电路在2.5 V供电电压下显示1 gbps /2线数据速率和35 mW功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC
A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis] 1.5 GHz OPAMP in 120nm digital CMOS Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM A 14-V high speed driver in 5-V-only 0.35-/spl mu/m standard CMOS A low-swing single-ended L1 cache bus technique for sub-90nm technologies
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1