{"title":"标准化测试结构设计","authors":"C. Weber","doi":"10.1109/ICMTS.1990.161730","DOIUrl":null,"url":null,"abstract":"A plan for standardization of test structure design based on a high-level information model is presented. The plan's implementation has dramatically improved the productivity of test chip layout, test software generation, data analysis, and documentation. Design errors, parametric test software defects, and documentation defects have been reduced to negligible levels.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"91 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Standardization of test structure design\",\"authors\":\"C. Weber\",\"doi\":\"10.1109/ICMTS.1990.161730\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A plan for standardization of test structure design based on a high-level information model is presented. The plan's implementation has dramatically improved the productivity of test chip layout, test software generation, data analysis, and documentation. Design errors, parametric test software defects, and documentation defects have been reduced to negligible levels.<<ETX>>\",\"PeriodicalId\":417292,\"journal\":{\"name\":\"Proceedings of the 1991 International Conference on Microelectronic Test Structures\",\"volume\":\"91 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1991 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1990.161730\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1990.161730","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A plan for standardization of test structure design based on a high-level information model is presented. The plan's implementation has dramatically improved the productivity of test chip layout, test software generation, data analysis, and documentation. Design errors, parametric test software defects, and documentation defects have been reduced to negligible levels.<>
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