Xinning Wang, Ranjith Kumar, S. Prakash, Peng Zheng, Tai-Hsuan Wu, Q. Shi, Marni Nabors, Srinivasa Chaitanya Gadigatla, S. Realov, Chin-Hsuan Chen, Ying Zhang, K. Mistry, A. Yeoh, I. Post, C. Auth, A. Madhavan
{"title":"Intel 10nm制程标准单元库的设计-技术协同优化","authors":"Xinning Wang, Ranjith Kumar, S. Prakash, Peng Zheng, Tai-Hsuan Wu, Q. Shi, Marni Nabors, Srinivasa Chaitanya Gadigatla, S. Realov, Chin-Hsuan Chen, Ying Zhang, K. Mistry, A. Yeoh, I. Post, C. Auth, A. Madhavan","doi":"10.1109/IEDM.2018.8614662","DOIUrl":null,"url":null,"abstract":"This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.","PeriodicalId":152963,"journal":{"name":"2018 IEEE International Electron Devices Meeting (IEDM)","volume":"526 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process\",\"authors\":\"Xinning Wang, Ranjith Kumar, S. Prakash, Peng Zheng, Tai-Hsuan Wu, Q. Shi, Marni Nabors, Srinivasa Chaitanya Gadigatla, S. Realov, Chin-Hsuan Chen, Ying Zhang, K. Mistry, A. Yeoh, I. Post, C. Auth, A. Madhavan\",\"doi\":\"10.1109/IEDM.2018.8614662\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.\",\"PeriodicalId\":152963,\"journal\":{\"name\":\"2018 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"526 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2018.8614662\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2018.8614662","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design-Technology Co-Optimization of Standard Cell Libraries on Intel 10nm Process
This paper highlights the co-optimization of process technology, std. cell library offerings and block-level TFM on Intel 10nm node to enable unprecedented scaling opportunity for products ranging from high performance client/server to low power mobile/IoT segments. The 10nm short height library enables 2.7x transistor density scaling going from 14nm counterpart. The taller height libraries are optimized to meet performance and reliability requirements of Intel's leading edge client/server products. PPA trade-offs are analyzed both at std. cell level and block level on an industry standard Core IP design.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
