{"title":"高速IO的模具SSN方法研究","authors":"Vinod Arjun Huddar","doi":"10.1109/EDAPS50281.2020.9312884","DOIUrl":null,"url":null,"abstract":"In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.","PeriodicalId":137699,"journal":{"name":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On Die SSN Methodology for High Speed IO\",\"authors\":\"Vinod Arjun Huddar\",\"doi\":\"10.1109/EDAPS50281.2020.9312884\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.\",\"PeriodicalId\":137699,\"journal\":{\"name\":\"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS50281.2020.9312884\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS50281.2020.9312884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we discuss the methodology of on-die simultaneous switching noise (SSN) simulation in high speed parallel bus like DDR5 associated with on-die capacitance and package inductance. The on-die supply ripple is typically larger than PCB power distribution network (PDN) noise even with a very good PCB PDN design. Resonance due to package inductance and on-die capacitance creates an impedance peak in the frequency domain and undesirable voltage noise in the time domain.
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