BiCMOS工艺中衬底电阻对隔离BJT Fmax参数的影响

ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307) Pub Date : 1999-03-15 DOI:10.1109/ICMTS.1999.766210

D. Gloria, A. Perrotin, J. Carbonéro, G. Morin

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引用次数: 7

摘要

介绍了具有几种保护环结构的双极器件的高频测试结构。利用这些结构，实验研究了衬底对性能参数Ft和Fmax的影响，并与微波设计系统(MDS)的电学模拟进行了比较。提出了保护环位置的最坏情况，提供高达15 GHz的Fmax退化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Substrate resistance effect on the Fmax parameter of isolated BJT in BiCMOS process

High frequency test structures for bipolar devices with several guard ring configurations are described. Using these structures, the substrate effect on merit figures such as Ft and Fmax has been studied experimentally and compared to Microwave Design System (MDS) electrical simulations. A worst case for guard ring position is proposed, providing up to 15 GHz Fmax degradation.

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ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)

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