用于0.8 μ m BiCMOS栅极阵列的快速ECL-to-CMOS和CMOS-to-ECL转换器

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186196

A. Bass, T.T. Eyck

{"title":"用于0.8 μ m BiCMOS栅极阵列的快速ECL-to-CMOS和CMOS-to-ECL转换器","authors":"A. Bass, T.T. Eyck","doi":"10.1109/ASIC.1990.186196","DOIUrl":null,"url":null,"abstract":"Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"581 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array\",\"authors\":\"A. Bass, T.T. Eyck\",\"doi\":\"10.1109/ASIC.1990.186196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"581 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186196\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

输入/输出电路的设计，从真正的ECL电平转换到CMOS电平，而不带来负电源电压在芯片上讨论。仅使用+5 V和地消除了芯片上同时具有+5 V和-5 V引起的击穿和寄生MOSFET问题。这些电路为0.8 μ m BiCMOS门阵列提供ECL接口，并且比目前可用的其他转换器快得多。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array

Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

自引率

0.00%

发文量

期刊最新文献

A development system for an SRAM-based user-reprogrammable gate array Automated CAE tools for full custom design of bipolar analog ASICs A 200 MHz 100 K ECL output buffer for CMOS ASICs Multi circular buffer controller chip for advanced ESM system Rapid prototyping, is there an educational dilemma? (ASIC design)