Key components of the fast reduced instruction set computer (FRISC) employing advanced bipolar differential logic and wafer scale multichip packaging

Advanced bipolar circuits for a RISC operating at a 250 MHz instruction rate are presented. Specifically a 30*8 bit register file macro with 500-ps access time is presented and a clock skew compensation scheme based on digital delay lines is introduced that can significantly reduce clock skew in a wafer scale multichip package. The predicted performance of advanced bipolar memory macros, I/O circuitry, and differential logic circuit are very encouraging. Measurement on a fabricated divide by two circuits shows good agreement with SPICE simulations.<>