具有高速结构的实验性5ns BiCMOS SRAM

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111086

K. Fung, T. Suzuki, J. Terazawa, A. Khayami, S. Martindell, C. Blanton, H. Tran, R. Eklund, S. Madan, T. Holloway, M. Rodder, J. Graham, R. Chapman, R. Haken, D. Scott

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引用次数: 4

摘要

描述了一种使用电路技术和架构创新来实现当今系统所要求的性能的RAM。该RAM采用了输入缓冲器/电平转换器、电流检测放大器和高速架构，实现了5ns的访问时间以及0.6 μ m的BiCMOS技术。该芯片采用28 μ m2的4T2R存储单元，组织为128 k字× 8-b宽

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An experimental 5 ns BiCMOS SRAM with a high-speed architecture

A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2

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Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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