{"title":"模拟在半导体制造中的应用","authors":"P. Deosthali, A. Gardel","doi":"10.1109/ASMC.1990.111215","DOIUrl":null,"url":null,"abstract":"The authors describe how the use of simulation technology captures the dynamics and interdependencies of very-large-scale-integration (VLSI) fabrication. A case study of a photolithography cell demonstrates how simulation is used to perform capacity planning to optimize the production line. The emphasis is on identifying the bottleneck areas and evaluating proposed changes to minimize the time to market of proprietary chips.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Using simulation in semiconductor fabrication\",\"authors\":\"P. Deosthali, A. Gardel\",\"doi\":\"10.1109/ASMC.1990.111215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe how the use of simulation technology captures the dynamics and interdependencies of very-large-scale-integration (VLSI) fabrication. A case study of a photolithography cell demonstrates how simulation is used to perform capacity planning to optimize the production line. The emphasis is on identifying the bottleneck areas and evaluating proposed changes to minimize the time to market of proprietary chips.<<ETX>>\",\"PeriodicalId\":158760,\"journal\":{\"name\":\"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop\",\"volume\":\"34 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.1990.111215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.1990.111215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The authors describe how the use of simulation technology captures the dynamics and interdependencies of very-large-scale-integration (VLSI) fabrication. A case study of a photolithography cell demonstrates how simulation is used to perform capacity planning to optimize the production line. The emphasis is on identifying the bottleneck areas and evaluating proposed changes to minimize the time to market of proprietary chips.<>
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