A new approach to gate stack integrity based on mechanical and electrostatic strain relief in self-organized interfacial suboxide transition regions

The purpose of this paper is to develop a physical model for the formation of self-organized, interfacial transition regions between Si and compound semiconductor substrates such as GaN, and SiO/sub 2/ and alternative high-k gate dielectrics. One objective is to identify i) why densities of interfacial Si dangling bonds prior to H-termination are larger by factors of 4-6 at Si-Al/sub 2/O/sub 3/ and Si-ZrO/sub 2/ interfaces compared to Si-SiO/sub 2/ and ii) why interfacial traps, D/sub it/, and C-V hysteresis are up to ten times larger. A second is to show that these interface traps are located in strained Si and GaN regions at their respective dielectric interfaces. The SHG phase angle versus change in film thickness plot for Si-SiO/sub 2/ structures is processed.