Koji Fukuda, G. Ono, K. Watanabe, T. Muto, H. Yamashita, N. Masuda, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, M. Kono, Akihiro Kambe, Seiichi Umai, T. Saito, S. Nishimura
{"title":"用于100千兆以太网链路的CMOS低功耗10:4 MUX和4:10 DEMUX变速箱IC","authors":"Koji Fukuda, G. Ono, K. Watanabe, T. Muto, H. Yamashita, N. Masuda, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, M. Kono, Akihiro Kambe, Seiichi Umai, T. Saito, S. Nishimura","doi":"10.1109/CSICS.2011.6062438","DOIUrl":null,"url":null,"abstract":"The world's first CMOS \"gearbox LSI\" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).","PeriodicalId":275064,"journal":{"name":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link\",\"authors\":\"Koji Fukuda, G. Ono, K. Watanabe, T. Muto, H. Yamashita, N. Masuda, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, M. Kono, Akihiro Kambe, Seiichi Umai, T. Saito, S. Nishimura\",\"doi\":\"10.1109/CSICS.2011.6062438\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The world's first CMOS \\\"gearbox LSI\\\" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).\",\"PeriodicalId\":275064,\"journal\":{\"name\":\"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2011.6062438\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2011.6062438","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
世界上第一个基于65纳米CMOS技术的CMOS“变速箱LSI”，即结合10:4多路复用器和4:10解路复用器的2 w 100千兆以太网变速箱LSI，被开发出来。它的功耗比传统的基于sig的齿轮箱LSI低75%。其12.5 Gb/s接口功耗为0.98 mW/(Gb/s)， 25gb /s接口功耗为14 mW/(Gb/s)。
A CMOS Low-Power 10:4 MUX and 4:10 DEMUX Gearbox IC for 100-Gigabit Ethernet Link
The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).
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