CMOS锁存滞后发射极电阻的光电识别

Ming-Jer Chen, J. Jeng, P. Tseng, N. Tsai, Ching-Yuan Wu
{"title":"CMOS锁存滞后发射极电阻的光电识别","authors":"Ming-Jer Chen, J. Jeng, P. Tseng, N. Tsai, Ching-Yuan Wu","doi":"10.1109/ICMTS.1990.161748","DOIUrl":null,"url":null,"abstract":"The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.<<ETX>>","PeriodicalId":417292,"journal":{"name":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Photoemission identification of emitter resistance for CMOS latch-up hysteresis\",\"authors\":\"Ming-Jer Chen, J. Jeng, P. Tseng, N. Tsai, Ching-Yuan Wu\",\"doi\":\"10.1109/ICMTS.1990.161748\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.<<ETX>>\",\"PeriodicalId\":417292,\"journal\":{\"name\":\"Proceedings of the 1991 International Conference on Microelectronic Test Structures\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1991 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1990.161748\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1991 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1990.161748","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

本文提出了一种应用于特殊设计的p-n-p-n结构的光电探测技术,以便准确地确定CMOS闭锁路径中控制I-V特性滞后的基本参数。实验和理论都表明,发射极电阻对磁滞的产生起着重要的作用。作者还描述了三维效应的针组合的迟滞的形成
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Photoemission identification of emitter resistance for CMOS latch-up hysteresis
The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.<>
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Trench DRAM structures for the analysis of two- and three-dimensional leakage phenomena The vertical test structure for measuring contact resistance between two kinds of metal An ovenless electromigration test system environment using test chips with on-chip heating and computer controlled testing Material and process learning by noncontact characterization of minority carrier lifetime and surface recombination condition Edge effect prediction in real MOS insulator using test chips
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1