{"title":"模拟数字asic的仿真考虑","authors":"P. Fasang","doi":"10.1109/ASIC.1990.186143","DOIUrl":null,"url":null,"abstract":"Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Simulation considerations for analog-digital ASICs\",\"authors\":\"P. Fasang\",\"doi\":\"10.1109/ASIC.1990.186143\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186143\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186143","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simulation considerations for analog-digital ASICs
Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<>