模拟数字asic的仿真考虑

P. Fasang
{"title":"模拟数字asic的仿真考虑","authors":"P. Fasang","doi":"10.1109/ASIC.1990.186143","DOIUrl":null,"url":null,"abstract":"Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Simulation considerations for analog-digital ASICs\",\"authors\":\"P. Fasang\",\"doi\":\"10.1109/ASIC.1990.186143\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<<ETX>>\",\"PeriodicalId\":126693,\"journal\":{\"name\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1990.186143\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186143","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了可测试性设计领域的问题和问题,以及如何将仿真输出映射到测试器。这些问题和问题是混合信号模拟数字ASIC设计人员今天遇到的。从过去的经验中得到了解决方案。适当考虑可测试性方面的设计和仿真方面的设计将使混合信号设计顺利进行,而不会延迟从设计到硅交付。如果没有适当的考虑,由于可测试性问题或不知道如何处理一些模拟输入或输出刺激,设计可能会被大大延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Simulation considerations for analog-digital ASICs
Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<>
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A development system for an SRAM-based user-reprogrammable gate array Automated CAE tools for full custom design of bipolar analog ASICs A 200 MHz 100 K ECL output buffer for CMOS ASICs Multi circular buffer controller chip for advanced ESM system Rapid prototyping, is there an educational dilemma? (ASIC design)
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1