{"title":"PC系统中的电磁干扰和供电设计","authors":"D. Herrell, B. Beker","doi":"10.1109/EPEP.1997.634029","DOIUrl":null,"url":null,"abstract":"This paper addresses the relationship of power transient design with the EMI characteristics of high-performance microprocessors. After a brief review of EMI and its role in modern PC systems, a modeling approach for a complete CPGA package is discussed. The model includes on-chip and on-package decoupling capacitors, multiple power and ground planes for core voltages, C4 bumps, inter-planar vias, and pins. Equivalent SPICE circuit for the chip-package combination is obtained and the results for power transients and frequency domain transfer characteristics are given.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"EMI and power delivery design in PC systems\",\"authors\":\"D. Herrell, B. Beker\",\"doi\":\"10.1109/EPEP.1997.634029\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper addresses the relationship of power transient design with the EMI characteristics of high-performance microprocessors. After a brief review of EMI and its role in modern PC systems, a modeling approach for a complete CPGA package is discussed. The model includes on-chip and on-package decoupling capacitors, multiple power and ground planes for core voltages, C4 bumps, inter-planar vias, and pins. Equivalent SPICE circuit for the chip-package combination is obtained and the results for power transients and frequency domain transfer characteristics are given.\",\"PeriodicalId\":220951,\"journal\":{\"name\":\"Electrical Performance of Electronic Packaging\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Performance of Electronic Packaging\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.1997.634029\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Performance of Electronic Packaging","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1997.634029","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper addresses the relationship of power transient design with the EMI characteristics of high-performance microprocessors. After a brief review of EMI and its role in modern PC systems, a modeling approach for a complete CPGA package is discussed. The model includes on-chip and on-package decoupling capacitors, multiple power and ground planes for core voltages, C4 bumps, inter-planar vias, and pins. Equivalent SPICE circuit for the chip-package combination is obtained and the results for power transients and frequency domain transfer characteristics are given.
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