一种用于DMOS晶体管通道长度提取的电容电压测量方法

J. Olsson, R. Valtonen, U. Heinle, L. Vestling, A. Soderbarg, H. Norde
{"title":"一种用于DMOS晶体管通道长度提取的电容电压测量方法","authors":"J. Olsson, R. Valtonen, U. Heinle, L. Vestling, A. Soderbarg, H. Norde","doi":"10.1109/ICMTS.1999.766231","DOIUrl":null,"url":null,"abstract":"This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.","PeriodicalId":273071,"journal":{"name":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A capacitance-voltage measurement method for DMOS transistor channel length extraction\",\"authors\":\"J. Olsson, R. Valtonen, U. Heinle, L. Vestling, A. Soderbarg, H. Norde\",\"doi\":\"10.1109/ICMTS.1999.766231\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.\",\"PeriodicalId\":273071,\"journal\":{\"name\":\"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1999.766231\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1999.766231","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16

摘要

本文报道了一种提取DMOS晶体管亚微米沟道长度的新测量方法。该方法基于栅极到源极、栅极到p基极和栅极到漏极电容的电容电压测量。在DMOS晶体管上测量到的通道长度为0.3 /spl mu/m。数值器件仿真和小信号电容仿真支持了结果和测量原理。
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A capacitance-voltage measurement method for DMOS transistor channel length extraction
This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.
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