R.K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang
{"title":"一个30v p沟道门控DMOSFET，在2.7 V时具有900 /spl mu//spl Omega/-cm/sup 2/比导通电阻","authors":"R.K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang","doi":"10.1109/ISPSD.1996.509447","DOIUrl":null,"url":null,"abstract":"A scaled-oxide low-threshold P-channel trench gated DMOS employing a 12 Mcell/in/sup 2/. (2 Mcell/cm/sup 2/) closed-cell design, 8-V gate rating and 30-V drain rating is described. Measured specific resistances of 900 /spl mu//spl Omega/-cm/sup 2/ at V/sub G/S=2.7 V and 700 /spl mu//spl Omega/-cm/sup 2/. At V/sub GS/=4.5 V represent the lowest R/sub DSA/ values ever reported for a P-channel DMOS with a 37-V breakdown. The benefit of a 3X scaling of gate oxide thickness is shown by measurement, analytical and numerical modeling to produce a 1.6-V reduction in threshold, a 75% reduction in channel resistance and a 45% reduction in overall trench DMOS on-resistance at V/sub GS/=4.5 V. High density 30-V planar DMOS die resistance is shown to be 3.7X that of the scaled-oxide trench DMOS at V/sub GS/=4.5 V.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 30-V P-channel trench gated DMOSFET with 900 /spl mu//spl Omega/-cm/sup 2/ specific on-resistance at 2.7 V\",\"authors\":\"R.K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang\",\"doi\":\"10.1109/ISPSD.1996.509447\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A scaled-oxide low-threshold P-channel trench gated DMOS employing a 12 Mcell/in/sup 2/. (2 Mcell/cm/sup 2/) closed-cell design, 8-V gate rating and 30-V drain rating is described. Measured specific resistances of 900 /spl mu//spl Omega/-cm/sup 2/ at V/sub G/S=2.7 V and 700 /spl mu//spl Omega/-cm/sup 2/. At V/sub GS/=4.5 V represent the lowest R/sub DSA/ values ever reported for a P-channel DMOS with a 37-V breakdown. The benefit of a 3X scaling of gate oxide thickness is shown by measurement, analytical and numerical modeling to produce a 1.6-V reduction in threshold, a 75% reduction in channel resistance and a 45% reduction in overall trench DMOS on-resistance at V/sub GS/=4.5 V. High density 30-V planar DMOS die resistance is shown to be 3.7X that of the scaled-oxide trench DMOS at V/sub GS/=4.5 V.\",\"PeriodicalId\":377997,\"journal\":{\"name\":\"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1996.509447\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1996.509447","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 30-V P-channel trench gated DMOSFET with 900 /spl mu//spl Omega/-cm/sup 2/ specific on-resistance at 2.7 V
A scaled-oxide low-threshold P-channel trench gated DMOS employing a 12 Mcell/in/sup 2/. (2 Mcell/cm/sup 2/) closed-cell design, 8-V gate rating and 30-V drain rating is described. Measured specific resistances of 900 /spl mu//spl Omega/-cm/sup 2/ at V/sub G/S=2.7 V and 700 /spl mu//spl Omega/-cm/sup 2/. At V/sub GS/=4.5 V represent the lowest R/sub DSA/ values ever reported for a P-channel DMOS with a 37-V breakdown. The benefit of a 3X scaling of gate oxide thickness is shown by measurement, analytical and numerical modeling to produce a 1.6-V reduction in threshold, a 75% reduction in channel resistance and a 45% reduction in overall trench DMOS on-resistance at V/sub GS/=4.5 V. High density 30-V planar DMOS die resistance is shown to be 3.7X that of the scaled-oxide trench DMOS at V/sub GS/=4.5 V.
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