A Novel CMOS Compatible Stacked Floating Gate Device Using TiN As A Control Gate

A TiN gate cladding layer, an integral part of an advanced ASIC CMOS process for resistance and Vth control, is selectively insulated from the underlying polysilicon gate by a thin dielectric to form a CMOS compatible floating gate transistor. The resulting stacked gate device is formed concurrent to the CMOS devices having essentially the same vertical profile. Device measurements indicate the new structure behaves electrically the same as conventional stacked double-polysilicon floating gate devices.