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引用次数: 5

摘要

1996年,全球集成电路产业规模达1400亿美元。随着消费电子产品和便携式电子产品市场的增长,这一市场也将增长。满足更高密度要求的组件封装需求。芯片级封装(CSP)解决了这一需求,但存在许多技术变体,使潜在用户对哪种技术适合其应用产生困惑。比较不同的包装技术是一项复杂的任务,涉及成本、性能和业务战略问题的优先级。本文只关注决策方程的一部分:成本。利用评估电子封装制造成本的工具,IBIS分析了几种芯片级封装技术的成本前景,包括晶圆级加工以及单个组件封装。本文考察了两种实现的成本,分析了它们对产品设计变量(即每个IC的I/ o数量和导通间距)和制造条件(即年产量和良率)的成本敏感性。
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Cost issues for chip scale packaging
The IC industry amounted to $140 billion worldwide in 1996. As the consumer and portable electronics portion of this market grows, so will. The demand for component packaging that meets higher density requirements. Chip scale packaging (CSP) addresses this need, but many technology variations exist, creating confusion among potential users about which technology may suit their application. Comparing alternative packaging technologies is a complex task, involving a prioritization of cost, performance, and business strategy issues. This paper focuses only one portion of the decision-making equation: cost. Using a tool for assessing the manufacturing cost of electronic packaging, IBIS has analyzed the cost outlook for several chip scale packaging technologies, including wafer-scale processing as well as individual component packaging. This paper examines the costs for both implementations, analyzing their cost sensitivity to product design variables (i.e., # of I/Os per IC and lead pitch) and manufacturing conditions (i.e., annual production volume and yield).
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