Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626961
M. Ikemizu, Y. Fukuzawa, J. Nakano, T. Yokoi, K. Miyajima, H. Funakura, E. Hosomi
The solder joint reliability for Chip Scale Package (CSP) as assembled on Printed Circuit Board (PCB) is believed to be poorer than that for QFP. The main cause of this poor reliability is the Coefficient of Thermal Expansion (CTE) mismatch between CSP and PCB. With a view to implement CSP into practical board assembly without underfill, we performed experimental study and FEM analysis of solder joint reliability for three different CSPs, among which two were ceramic fine-pitched ball grid arrays (C-FBGAs) and one plastic package (P-FBGA). We found that solder ball life predictions from the FEM analysis coupled with Coffin-Manson's equation were in good agreement with results from reliability experiments for C-FBGA (high-a) and P-FBGA, whereas difference between them was observed in the case of C-FBGA (Al/sub 2/O/sub 3/). Among three CSPs, P-FBGA turned out to have excellent solder fatigue life and there is the prospect it can be implemented in board assembly without underfill.
{"title":"CSP solder ball reliability","authors":"M. Ikemizu, Y. Fukuzawa, J. Nakano, T. Yokoi, K. Miyajima, H. Funakura, E. Hosomi","doi":"10.1109/IEMT.1997.626961","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626961","url":null,"abstract":"The solder joint reliability for Chip Scale Package (CSP) as assembled on Printed Circuit Board (PCB) is believed to be poorer than that for QFP. The main cause of this poor reliability is the Coefficient of Thermal Expansion (CTE) mismatch between CSP and PCB. With a view to implement CSP into practical board assembly without underfill, we performed experimental study and FEM analysis of solder joint reliability for three different CSPs, among which two were ceramic fine-pitched ball grid arrays (C-FBGAs) and one plastic package (P-FBGA). We found that solder ball life predictions from the FEM analysis coupled with Coffin-Manson's equation were in good agreement with results from reliability experiments for C-FBGA (high-a) and P-FBGA, whereas difference between them was observed in the case of C-FBGA (Al/sub 2/O/sub 3/). Among three CSPs, P-FBGA turned out to have excellent solder fatigue life and there is the prospect it can be implemented in board assembly without underfill.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1056 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123157290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626897
M. Riedlin, Nduka Nnamdi (Ndy) Ekere
Like most solids in liquid suspensions at high solid volume fraction, solder paste exhibits very complicated rheological behaviour. Many rheological characteristics, such as shear thinning, pseudoplasticity, and thixotropy are observed in this material. These characteristics are known to have different impacts on the solder paste's primary application: stencil printing. In fact, at various stages of the printing process, different and sometimes conflicting rheological characteristics ate required of the solder paste. These characteristics have been receiving increasing attention in the solder paste literature. However, one rheological property that has been overlooked is the normal stresses generated in the solder paste. These two stresses are the normal components to the shear stress. These stresses are only found in non-Newtonian materials and are part of its non-linear viscoelastic properties. This paper describes a methodology to measure the normal stress differences of solder paste under steady shear. In the method used to measure the normal stresses, a special type of rheometer, known as a rheogoniometer is used. For comparative normal stress measurements, only certain types of geometries can be used for solder paste. A typical shear rate experiment is described using cone and plate, and parallel plate geometries. Potential errors in the measurements of normal stress differences are also discussed.
{"title":"Rheological techniques for measuring normal stress differences of solder paste [PCBs]","authors":"M. Riedlin, Nduka Nnamdi (Ndy) Ekere","doi":"10.1109/IEMT.1997.626897","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626897","url":null,"abstract":"Like most solids in liquid suspensions at high solid volume fraction, solder paste exhibits very complicated rheological behaviour. Many rheological characteristics, such as shear thinning, pseudoplasticity, and thixotropy are observed in this material. These characteristics are known to have different impacts on the solder paste's primary application: stencil printing. In fact, at various stages of the printing process, different and sometimes conflicting rheological characteristics ate required of the solder paste. These characteristics have been receiving increasing attention in the solder paste literature. However, one rheological property that has been overlooked is the normal stresses generated in the solder paste. These two stresses are the normal components to the shear stress. These stresses are only found in non-Newtonian materials and are part of its non-linear viscoelastic properties. This paper describes a methodology to measure the normal stress differences of solder paste under steady shear. In the method used to measure the normal stresses, a special type of rheometer, known as a rheogoniometer is used. For comparative normal stress measurements, only certain types of geometries can be used for solder paste. A typical shear rate experiment is described using cone and plate, and parallel plate geometries. Potential errors in the measurements of normal stress differences are also discussed.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127204670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626954
Wanzhen Huang, Shanling Li
In this paper, we consider a two-stage hybrid flowshop in a semi-conductor industry. We assume that components are grouped into families and a major setup is required when a machine at either stage starts to process a new family. While Stage 1 contains a single machine, Stage 2 contains multiple uniform machines. The objective is to minimize the total makespan. To solve the problem, we develop a heuristic and 8 effective sequencing rules to assign the parts to the machines at both stages. We also present a model to examine the trade-offs between the costs and the speeds of the machines at Stage 2. We also present a model to examine the trade-offs between the costs and the speeds of the machines at Stage 2.
{"title":"A two-stage hybrid with uniform machines and setup times","authors":"Wanzhen Huang, Shanling Li","doi":"10.1109/IEMT.1997.626954","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626954","url":null,"abstract":"In this paper, we consider a two-stage hybrid flowshop in a semi-conductor industry. We assume that components are grouped into families and a major setup is required when a machine at either stage starts to process a new family. While Stage 1 contains a single machine, Stage 2 contains multiple uniform machines. The objective is to minimize the total makespan. To solve the problem, we develop a heuristic and 8 effective sequencing rules to assign the parts to the machines at both stages. We also present a model to examine the trade-offs between the costs and the speeds of the machines at Stage 2. We also present a model to examine the trade-offs between the costs and the speeds of the machines at Stage 2.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122323935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626928
Wang Tingyue, Cui Dianheng, Yu Shenlin, Tang Jun, Y. Wei
The operation frequency of Transmit/Receive (T/R) module for active phased-array radar is very high (at least above 1000 MHz). The ground connection between the back side metal plating of the functional elements and the substrate carrier of the T/R module is so important that it can directly affect the performance and reliability of the functional elements and T/R module. In this paper, the following techniques are studied: conduction and reliability of the via hole between top side and back side of the thin film or thick film microwave circuit substrate, control of soldering stress and deformations; solderability of available materials; and soldering processing technology. Highly reliable T/R modules are successfully manufactured by using soldering in place of screws.
{"title":"Ground connection soldering techniques of high density ceramics substrate of transmit/receive module and its reliability","authors":"Wang Tingyue, Cui Dianheng, Yu Shenlin, Tang Jun, Y. Wei","doi":"10.1109/IEMT.1997.626928","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626928","url":null,"abstract":"The operation frequency of Transmit/Receive (T/R) module for active phased-array radar is very high (at least above 1000 MHz). The ground connection between the back side metal plating of the functional elements and the substrate carrier of the T/R module is so important that it can directly affect the performance and reliability of the functional elements and T/R module. In this paper, the following techniques are studied: conduction and reliability of the via hole between top side and back side of the thin film or thick film microwave circuit substrate, control of soldering stress and deformations; solderability of available materials; and soldering processing technology. Highly reliable T/R modules are successfully manufactured by using soldering in place of screws.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130390808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626957
Yi-Feng Hung, Ching-Bin Chang
This study examined two dispatch rules-modified least slack rule and shortest remaining flow time rule. Both of these rules require future flow time prediction. We experimented with two flow time prediction methods-an exponential smoothing method and an iterative empirical curve approach. These new rules were compared with some other commonly used rules by simulation experiment. For the performance measure of mean flow time, the shortest remaining processing time rule performed best. Whereas, for the performance measure of standard deviation of flow time, the modified least slack rule with the flow time prediction by the iterative empirical curve approach performed best.
{"title":"A study of wafer fab dispatching rules based on empirical flow time predictions","authors":"Yi-Feng Hung, Ching-Bin Chang","doi":"10.1109/IEMT.1997.626957","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626957","url":null,"abstract":"This study examined two dispatch rules-modified least slack rule and shortest remaining flow time rule. Both of these rules require future flow time prediction. We experimented with two flow time prediction methods-an exponential smoothing method and an iterative empirical curve approach. These new rules were compared with some other commonly used rules by simulation experiment. For the performance measure of mean flow time, the shortest remaining processing time rule performed best. Whereas, for the performance measure of standard deviation of flow time, the modified least slack rule with the flow time prediction by the iterative empirical curve approach performed best.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128094166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626943
W. Trybula
The semiconductor industry growth continues to be driven to a large extent by steady advancements in microlithography. The SIA Roadmap renewal is underway and "work-in-process" predicts accelerating requirements. The 130 nm generation is anticipated to be needed in the year 2003, with the 100 nm generation 3 years later...the path to get there is not obvious! With a potential end to traditional optical lithography, the choices among Extreme Ultraviolet (EUV or soft X-ray), ion beam, projection e-beam, proximity X-ray, or alternative reflective technology is not obvious or guaranteed for success in the time required. The goal is to make a data-driven decision by late 1997. As the concluding paper in this special section on Lithography, this work will look at the implications of entering into a new technology as the industry attempts to maintain the historic growth curve-also called staying on the roadmap. The purpose of this paper is look at the issues and raise the questions that need to be considered before moving to a new technology.
{"title":"Next generation lithography-implications","authors":"W. Trybula","doi":"10.1109/IEMT.1997.626943","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626943","url":null,"abstract":"The semiconductor industry growth continues to be driven to a large extent by steady advancements in microlithography. The SIA Roadmap renewal is underway and \"work-in-process\" predicts accelerating requirements. The 130 nm generation is anticipated to be needed in the year 2003, with the 100 nm generation 3 years later...the path to get there is not obvious! With a potential end to traditional optical lithography, the choices among Extreme Ultraviolet (EUV or soft X-ray), ion beam, projection e-beam, proximity X-ray, or alternative reflective technology is not obvious or guaranteed for success in the time required. The goal is to make a data-driven decision by late 1997. As the concluding paper in this special section on Lithography, this work will look at the implications of entering into a new technology as the industry attempts to maintain the historic growth curve-also called staying on the roadmap. The purpose of this paper is look at the issues and raise the questions that need to be considered before moving to a new technology.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131342543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626887
T. Aanstoos, I. Braithwaite, J. House, D. Robinson, S. Nichols
As computers and their components progress in technology, useful life shortens, leading to large volumes of equipment facing disposition. Used cathode ray tubes especially pose environmental risks due to their lead content. Effective recycling of CRT glass requires an economical disassembly process that results in well-identified and separated glass that meets quality needs for use in new CRTs. A senior student design team studied the problem of how to separate CRT tubes with minimum time and cost, and minimum hazard due to exposure to lead. Laboratory experiments were conducted on four concept variants and the results were analyzed. The design team concluded that diamond cutting of the panel from the funnel, and removal of coatings by plastic media blasting, is the best method studied.
{"title":"Disassembly process far a cathode ray tube","authors":"T. Aanstoos, I. Braithwaite, J. House, D. Robinson, S. Nichols","doi":"10.1109/IEMT.1997.626887","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626887","url":null,"abstract":"As computers and their components progress in technology, useful life shortens, leading to large volumes of equipment facing disposition. Used cathode ray tubes especially pose environmental risks due to their lead content. Effective recycling of CRT glass requires an economical disassembly process that results in well-identified and separated glass that meets quality needs for use in new CRTs. A senior student design team studied the problem of how to separate CRT tubes with minimum time and cost, and minimum hazard due to exposure to lead. Laboratory experiments were conducted on four concept variants and the results were analyzed. The design team concluded that diamond cutting of the panel from the funnel, and removal of coatings by plastic media blasting, is the best method studied.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124143340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626883
S. Giegling, W.A. Verdini, T. Haymon, J. Konopka
Factory capacity is becoming exceedingly expensive and new factories may not reach designed output levels for at least a couple of years. In the semiconductor industry, required investments in new wafer fabrication facilities may exceed $1 billion. As the cost of semiconductor manufacturing facilities continues to escalate and profit margins get squeezed, semiconductor manufacturers must attempt to increase production capabilities in their existing semiconductor manufacturing facilities (FABs). Assessing the utilization of existing capacity is a key component in this effort. One capacity analysis tool that is currently in use within the RF1 wafer fabrication facility of Motorola's Semiconductor Products Sector (SPS) is the Capacity Utilization Bottleneck Efficiency System (CUBES). RF1 is using CUBES to enhance a very progressive Total Productive Manufacturing (TPM) program. CUBES was gradually introduced to RF1 during the summer of 1995 and became widely accepted during the Fall of 1995 after an interface between CUBES and the work in process (WIP) tracking system, PROMIS/sup TM/, was established. The CUBES decision support tool is generally simple to use, but collecting the input tool performance data may be difficult and time consuming. Since direct users of CUBES range from managers to maintenance technicians to operators, it was imperative to develop a system that linked necessary databases together automatically to calculate capacity and Overall Equipment Effectiveness (OEE). This paper discusses the implementation process. To acquaint the reader, we begin with a brief review of the objectives of this project. Following that is a discussion of the components and implementation of this system.
{"title":"Implementation of overall equipment effectiveness (OEE) system at a semiconductor manufacturer","authors":"S. Giegling, W.A. Verdini, T. Haymon, J. Konopka","doi":"10.1109/IEMT.1997.626883","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626883","url":null,"abstract":"Factory capacity is becoming exceedingly expensive and new factories may not reach designed output levels for at least a couple of years. In the semiconductor industry, required investments in new wafer fabrication facilities may exceed $1 billion. As the cost of semiconductor manufacturing facilities continues to escalate and profit margins get squeezed, semiconductor manufacturers must attempt to increase production capabilities in their existing semiconductor manufacturing facilities (FABs). Assessing the utilization of existing capacity is a key component in this effort. One capacity analysis tool that is currently in use within the RF1 wafer fabrication facility of Motorola's Semiconductor Products Sector (SPS) is the Capacity Utilization Bottleneck Efficiency System (CUBES). RF1 is using CUBES to enhance a very progressive Total Productive Manufacturing (TPM) program. CUBES was gradually introduced to RF1 during the summer of 1995 and became widely accepted during the Fall of 1995 after an interface between CUBES and the work in process (WIP) tracking system, PROMIS/sup TM/, was established. The CUBES decision support tool is generally simple to use, but collecting the input tool performance data may be difficult and time consuming. Since direct users of CUBES range from managers to maintenance technicians to operators, it was imperative to develop a system that linked necessary databases together automatically to calculate capacity and Overall Equipment Effectiveness (OEE). This paper discusses the implementation process. To acquaint the reader, we begin with a brief review of the objectives of this project. Following that is a discussion of the components and implementation of this system.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123982122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626870
S. Yegnasubramanian, R. Deshmukh, J. Fulton, R. Fanucci, J. Gannon, J. R. Morris, K. Nikmanesh
This paper discusses the methods of direct chip attachment (DCA) and the results of interconnect reliability qualification of flip chip assemblies with underfill. The method developed provides a 'dropin' surface mount process to attach bumped silicon devices to laminates utilizing standard surface mount assembly equipment. Assemblies of test vehicles and product modules demonstrated satisfactory results in all of the reliability qualification and product conformance criteria. Results of failure mode analysis (FMA) of assemblies subjected to thermal stress are discussed.
{"title":"Flip-chip-on-board (FCOB) assembly and reliability","authors":"S. Yegnasubramanian, R. Deshmukh, J. Fulton, R. Fanucci, J. Gannon, J. R. Morris, K. Nikmanesh","doi":"10.1109/IEMT.1997.626870","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626870","url":null,"abstract":"This paper discusses the methods of direct chip attachment (DCA) and the results of interconnect reliability qualification of flip chip assemblies with underfill. The method developed provides a 'dropin' surface mount process to attach bumped silicon devices to laminates utilizing standard surface mount assembly equipment. Assemblies of test vehicles and product modules demonstrated satisfactory results in all of the reliability qualification and product conformance criteria. Results of failure mode analysis (FMA) of assemblies subjected to thermal stress are discussed.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129771671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-13DOI: 10.1109/IEMT.1997.626962
D. Mendez
Successful processing of high pin count Ball Grid Array (BGA) components through an assembly operation is dependant upon many factors including solder paste deposition, component placement, and quality of the raw materials including the printed wiring boards (PWB) and the BGA components.
{"title":"High pin count BGA board level assembly","authors":"D. Mendez","doi":"10.1109/IEMT.1997.626962","DOIUrl":"https://doi.org/10.1109/IEMT.1997.626962","url":null,"abstract":"Successful processing of high pin count Ball Grid Array (BGA) components through an assembly operation is dependant upon many factors including solder paste deposition, component placement, and quality of the raw materials including the printed wiring boards (PWB) and the BGA components.","PeriodicalId":227971,"journal":{"name":"Twenty First IEEE/CPMT International Electronics Manufacturing Technology Symposium Proceedings 1997 IEMT Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127085722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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