无掺杂薄膜FD-SOI CMOS，具有源极漏极非重叠结构，适用于超低泄漏应用

2005 IEEE International SOI Conference Proceedings Pub Date : 2005-12-27 DOI:10.1109/SOI.2005.1563579

N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida

{"title":"无掺杂薄膜FD-SOI CMOS，具有源极漏极非重叠结构，适用于超低泄漏应用","authors":"N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida","doi":"10.1109/SOI.2005.1563579","DOIUrl":null,"url":null,"abstract":"In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Undoped thin film FD-SOI CMOS with source/drain-to-gate non-overlapped structure for ultra low leak applications\",\"authors\":\"N. Miura, Y. Domae, T. Sakata, M. Watanabe, T. Okamura, T. Chiba, K. Fukuda, J. Ida\",\"doi\":\"10.1109/SOI.2005.1563579\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.\",\"PeriodicalId\":116606,\"journal\":{\"name\":\"2005 IEEE International SOI Conference Proceedings\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2005.1563579\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563579","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 11

摘要

在本文中，我们提出了一种无掺杂薄膜完全耗尽(FD)绝缘体上硅(SOI) CMOS，具有源/漏极到栅非重叠结构，用于超低漏(ULL)晶体管。该器件的截止频率f/sub /为65GHz, I/sub off/< 0.1pA//spl mu/m(无gidl)。所提出的反栅注入/平面型SOI是一种实用且低成本的硬币电池解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Undoped thin film FD-SOI CMOS with source/drain-to-gate non-overlapped structure for ultra low leak applications

In this paper, we present an undoped thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS with source/drain-to-gate non-overlapped structure for ultra low leak (ULL) transistor. The fabricated device achieved a cutoff frequency f/sub T/ of 65GHz with I/sub off/< 0.1pA//spl mu/m (GIDL-free). The proposed inverted-gate implantation/planar-type SOI is practical and low-cost solution for coin-battery applications.

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2005 IEEE International SOI Conference Proceedings

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