低功耗SoC内存BIST

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2006-10-04 DOI:10.1109/DFT.2006.39

Yuejian Wu, A. Ivanov

{"title":"低功耗SoC内存BIST","authors":"Yuejian Wu, A. Ivanov","doi":"10.1109/DFT.2006.39","DOIUrl":null,"url":null,"abstract":"With the ever increasing number of memories embedded in a system-on-chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Low Power SoC Memory BIST\",\"authors\":\"Yuejian Wu, A. Ivanov\",\"doi\":\"10.1109/DFT.2006.39\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the ever increasing number of memories embedded in a system-on-chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead\",\"PeriodicalId\":113870,\"journal\":{\"name\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2006.39\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2006.39","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 16

摘要

随着片上系统(SoC)中嵌入的存储器数量的不断增加，由于测试而导致的功耗已成为一个严重的问题。本文研究了sram的功耗，提出了一种新型的低功耗存储器BIST。在130纳米和90纳米技术的存储器上评估了其有效性。如图所示，在几乎为零硬件开销的情况下，可以实现高达30%的功耗降低

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Low Power SoC Memory BIST

With the ever increasing number of memories embedded in a system-on-chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

自引率

0.00%

发文量