{"title":"用于Zigbee频率合成器的CMOS可编程分压器","authors":"N. M. Ismail, M. Othman","doi":"10.1109/ICSCS.2009.5412594","DOIUrl":null,"url":null,"abstract":"This paper presents 4-bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a 15/16 dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock and consumes 0.7 mW. It is tested in PLL for 2.4GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18-µm CMOS process, and voltage supply 1.8V.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"CMOS programmable divider for Zigbee frequency synthesizer\",\"authors\":\"N. M. Ismail, M. Othman\",\"doi\":\"10.1109/ICSCS.2009.5412594\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents 4-bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a 15/16 dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock and consumes 0.7 mW. It is tested in PLL for 2.4GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18-µm CMOS process, and voltage supply 1.8V.\",\"PeriodicalId\":126072,\"journal\":{\"name\":\"2009 3rd International Conference on Signals, Circuits and Systems (SCS)\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 3rd International Conference on Signals, Circuits and Systems (SCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSCS.2009.5412594\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCS.2009.5412594","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS programmable divider for Zigbee frequency synthesizer
This paper presents 4-bit integer N CMOS programmable frequency divider with high speed and low power consumption. It is based on a 15/16 dual-modulus prescaler, and programmable asynchronous and synchronous dividers. It works up to 3.4 GHz frequency clock and consumes 0.7 mW. It is tested in PLL for 2.4GHz band Zigbee standard. All results are taken from simulating extracted layout. It is implemented using Silterra 0.18-µm CMOS process, and voltage supply 1.8V.
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