{"title":"在ESD设计布局中建立可靠性","authors":"T. Yeoh","doi":"10.1109/IPFA.1997.638192","DOIUrl":null,"url":null,"abstract":"Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Building in reliability during ESD design layout\",\"authors\":\"T. Yeoh\",\"doi\":\"10.1109/IPFA.1997.638192\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential.\",\"PeriodicalId\":159177,\"journal\":{\"name\":\"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-07-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.1997.638192\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.1997.638192","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Building in reliability during ESD design layout is key to the success of product design and development. Due to the limitations of automated layout checkers for ESD, knowledge of fundamental device physics, ESD and stress environments are essential.
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