基于蒙特卡罗仿真的集成CMOS工艺和设计对软错误率的影响研究

2008 IEEE International Reliability Physics Symposium Pub Date : 2008-07-09 DOI:10.1109/RELPHY.2008.4559010

C. Weulersse, A. Bougerol, G. Hubert, F. Wrobel, T. Carrière, R. Gaillard, N. Buard

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引用次数: 8

摘要

这项工作显示了基于核数据库的蒙特卡罗模拟的能力，以确定器件参数和工艺对集成体和SOI CMOS技术中高达65 nm的单细胞和多细胞扰流率的影响。该方法既适用于SRAM，也适用于逻辑单元，对高能和热中子也有效。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Investigation of the influence of process and design on soft error rate in integrated CMOS technologies thanks to Monte Carlo simulation

This work shows the capabilities of Monte Carlo simulation based on nuclear database to identify the influence of device parameters and process on Single Cell Upset and Multicell Upset rates in integrated bulk and SOI CMOS technologies up to 65 nm. The method is applicable both to SRAM and logic cells, and is valid for high energy and thermal neutrons.

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2008 IEEE International Reliability Physics Symposium

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