一种新的设计方法，使用仿真的片上ESD保护设计集成电路

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-10-21 DOI:10.1109/ICSICT.1998.785933

A. Wang, C. Tsay

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引用次数: 12

摘要

采用全尺寸混合模式仿真方法，为集成电路片上ESD保护设计开发了一种新的设计方法。讨论了完整的设计过程和设计实例，并在应用该设计方法时取得了较好的设计预测效果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new design methodology using simulation for on-chip ESD protection designs for integrated circuits

A new design methodology was developed for IC on-chip ESD protection design using a full-scale, mixed-mode simulation approach. The complete design procedure and design examples are discussed and reasonably good design prediction was observed in using this novel design methodology.

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1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)

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