Stress-aware analog layout devices pattern generation

This paper presents a stress-aware transistors layout pattern generation flow. For a given set of transistors with different finger unit ratios, and a set of user specified devices pattern together with the DC operating point for each device in the pattern, an Absolute Mismatch Factor (AMF) is provided. AMF presents the degree of matching between the devices in the pattern taking Shallow Trench Isolation (STI) into consideration. Multiple stacks are placed in a matrix-like layout recommended by recent technology nodes. The flow goal is to help the designer achieve a pattern with minimum AMF i.e. best matching, while avoiding multiple expensive iterations of layout design, extraction and post-layout simulations. Examples include multi-finger current mirror designs in a 65nm process. Post-layout simulations are finally used to demonstrate the results.