Koichi Tanaka, K. Fujimoto, E. Katsumata, T. Yaguchi, K. Tamaru, A. Kanuma, S. Iida, A. Nishikawa, H. Shiraishi, T. Mineoka, T. Shimamura
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VLSI architecture for IEEE 802.5 token-ring LAN controller
A description is given of the architecture of the token-ring LAN controller (TRC) compatible with IEEE 802.5 media access control (MAC) protocol, which integrates a frame transmit/receive hardware, a high-speed protocol processor, a three-channel DMA controller (DMAC) and large-capacity dual-port RAMs. The performance analysis of the frame transmit/receive shows that the TRC is suitable not only for small computers, but also for high-performance applications
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