I. Kitagawa, R. Baumann, I. Takigasaki, K. Maeda, Y. Ohashi, Y. Kikuchi, S. Murata
{"title":"通道热载流子对PMOS亚微米晶体管可靠性的影响","authors":"I. Kitagawa, R. Baumann, I. Takigasaki, K. Maeda, Y. Ohashi, Y. Kikuchi, S. Murata","doi":"10.1109/IPFA.1997.638173","DOIUrl":null,"url":null,"abstract":"Channel hot carrier (CHC) effects in PMOS transistors increase the drive current and reduce the threshold voltage (Vt). While these changes improve the device switching speed, the decreased Vt renders the transistor harder to \"turn off\". This work focused on defining the punch through voltage (BVDSS) of PMOS transistors from a CMOS submicron process as a function of gate length and stress voltage. A model and predictions of PMOS device lifetimes based on the CHC-induced BVDSS degradation is presented.","PeriodicalId":159177,"journal":{"name":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Channel hot carrier impact on the reliability performance of PMOS submicron transistors\",\"authors\":\"I. Kitagawa, R. Baumann, I. Takigasaki, K. Maeda, Y. Ohashi, Y. Kikuchi, S. Murata\",\"doi\":\"10.1109/IPFA.1997.638173\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Channel hot carrier (CHC) effects in PMOS transistors increase the drive current and reduce the threshold voltage (Vt). While these changes improve the device switching speed, the decreased Vt renders the transistor harder to \\\"turn off\\\". This work focused on defining the punch through voltage (BVDSS) of PMOS transistors from a CMOS submicron process as a function of gate length and stress voltage. A model and predictions of PMOS device lifetimes based on the CHC-induced BVDSS degradation is presented.\",\"PeriodicalId\":159177,\"journal\":{\"name\":\"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-07-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.1997.638173\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1997 6th International Symposium on the Physical and Failure Analysis of Integrated Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.1997.638173","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Channel hot carrier impact on the reliability performance of PMOS submicron transistors
Channel hot carrier (CHC) effects in PMOS transistors increase the drive current and reduce the threshold voltage (Vt). While these changes improve the device switching speed, the decreased Vt renders the transistor harder to "turn off". This work focused on defining the punch through voltage (BVDSS) of PMOS transistors from a CMOS submicron process as a function of gate length and stress voltage. A model and predictions of PMOS device lifetimes based on the CHC-induced BVDSS degradation is presented.