针对seu和set的在线加固程序

C. Lisbôa, L. Carro, M. Reorda, M. Violante
{"title":"针对seu和set的在线加固程序","authors":"C. Lisbôa, L. Carro, M. Reorda, M. Violante","doi":"10.1109/DFT.2006.49","DOIUrl":null,"url":null,"abstract":"Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability. However, SIHFT increases the time for running the hardened application, and the memory occupation. In this paper we propose a method that eliminates the memory overhead, using a new approach to instruction hardening and control flow checking during the execution of the application, without the need for introducing any change in its source code. The proposed method is also non-intrusive, since it does not require any modification in the main processor's architecture. The method is suitable for hardening SoCs against transient faults and also for detecting permanent faults","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Online hardening of programs against SEUs and SETs\",\"authors\":\"C. Lisbôa, L. Carro, M. Reorda, M. Violante\",\"doi\":\"10.1109/DFT.2006.49\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability. However, SIHFT increases the time for running the hardened application, and the memory occupation. In this paper we propose a method that eliminates the memory overhead, using a new approach to instruction hardening and control flow checking during the execution of the application, without the need for introducing any change in its source code. The proposed method is also non-intrusive, since it does not require any modification in the main processor's architecture. The method is suitable for hardening SoCs against transient faults and also for detecting permanent faults\",\"PeriodicalId\":113870,\"journal\":{\"name\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2006.49\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2006.49","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

嵌入在片上系统(soc)中的处理器内核经常被部署在关键计算中,当它们受到故障影响时可能会产生巨大的影响。当硬件加固不具有成本效益时,软件实现的硬件容错(SIHFT)可以作为提高soc可靠性的解决方案。但是,SIHFT增加了运行加固后的应用程序的时间和内存占用。在本文中,我们提出了一种消除内存开销的方法,在应用程序执行期间使用一种新的方法来加强指令和控制流检查,而不需要在其源代码中引入任何更改。所提出的方法也是非侵入性的,因为它不需要对主处理器的体系结构进行任何修改。该方法既适用于soc的瞬态故障加固,也适用于检测永久故障
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Online hardening of programs against SEUs and SETs
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability. However, SIHFT increases the time for running the hardened application, and the memory occupation. In this paper we propose a method that eliminates the memory overhead, using a new approach to instruction hardening and control flow checking during the execution of the application, without the need for introducing any change in its source code. The proposed method is also non-intrusive, since it does not require any modification in the main processor's architecture. The method is suitable for hardening SoCs against transient faults and also for detecting permanent faults
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