{"title":"矩阵型VLSI封装级可靠性问题的解决方法","authors":"I. Vasiltsov, B. Mandziy, A. Bench","doi":"10.1109/MIEL.2002.1003355","DOIUrl":null,"url":null,"abstract":"In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in choosing of the special area in the chip during mapping procedure at the packaging level. Usage of such approach allows for the designer to obtain a more optimal topology solution, and thus will increase the reliability of designed devices.","PeriodicalId":221518,"journal":{"name":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Approach to solve the reliability problem at packaging level in the matrix VLSI\",\"authors\":\"I. Vasiltsov, B. Mandziy, A. Bench\",\"doi\":\"10.1109/MIEL.2002.1003355\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in choosing of the special area in the chip during mapping procedure at the packaging level. Usage of such approach allows for the designer to obtain a more optimal topology solution, and thus will increase the reliability of designed devices.\",\"PeriodicalId\":221518,\"journal\":{\"name\":\"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIEL.2002.1003355\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIEL.2002.1003355","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Approach to solve the reliability problem at packaging level in the matrix VLSI
In this paper the problem of increasing the reliability of the designed devices, implemented on the matrix VLSI has been considered. The proposed approach consists in choosing of the special area in the chip during mapping procedure at the packaging level. Usage of such approach allows for the designer to obtain a more optimal topology solution, and thus will increase the reliability of designed devices.
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