H. Ichino, M. Suzuki, S. Konaka, T. Wakimoto, T. Sakai
{"title":"超自对准工艺技术及其应用","authors":"H. Ichino, M. Suzuki, S. Konaka, T. Wakimoto, T. Sakai","doi":"10.1109/BIPOL.1988.51034","DOIUrl":null,"url":null,"abstract":"SST-1B technology, an advanced version of SST-1A, and its applications are described. The main feature is utilization of the selectively ion-implanted collector process to improve shallow base-collector profiles to reduce base width and intrinsic base resistance, and to suppress the base pushout effect. A cutoff frequency of 25.7 GHz and the basic gate delays of 20.5 ps for NTL and 34.1 ps for ECL have been obtained. Using this technology, a number of very high-speed ICs-a 18-GHz 1/8 divider, a 2-Gbsps 6-bit AD converter, and 43-ps/5.2-GHz macrocell array LSIs-have been developed. Concerning future performance, a cutoff frequency of more than 50 GHz for a scaled-down transistor is expected.<<ETX>>","PeriodicalId":302949,"journal":{"name":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","volume":"165 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Super self-aligned process technology (SST) and its applications\",\"authors\":\"H. Ichino, M. Suzuki, S. Konaka, T. Wakimoto, T. Sakai\",\"doi\":\"10.1109/BIPOL.1988.51034\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SST-1B technology, an advanced version of SST-1A, and its applications are described. The main feature is utilization of the selectively ion-implanted collector process to improve shallow base-collector profiles to reduce base width and intrinsic base resistance, and to suppress the base pushout effect. A cutoff frequency of 25.7 GHz and the basic gate delays of 20.5 ps for NTL and 34.1 ps for ECL have been obtained. Using this technology, a number of very high-speed ICs-a 18-GHz 1/8 divider, a 2-Gbsps 6-bit AD converter, and 43-ps/5.2-GHz macrocell array LSIs-have been developed. Concerning future performance, a cutoff frequency of more than 50 GHz for a scaled-down transistor is expected.<<ETX>>\",\"PeriodicalId\":302949,\"journal\":{\"name\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"volume\":\"165 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1988.51034\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1988 Bipolar Circuits and Technology Meeting,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1988.51034","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Super self-aligned process technology (SST) and its applications
SST-1B technology, an advanced version of SST-1A, and its applications are described. The main feature is utilization of the selectively ion-implanted collector process to improve shallow base-collector profiles to reduce base width and intrinsic base resistance, and to suppress the base pushout effect. A cutoff frequency of 25.7 GHz and the basic gate delays of 20.5 ps for NTL and 34.1 ps for ECL have been obtained. Using this technology, a number of very high-speed ICs-a 18-GHz 1/8 divider, a 2-Gbsps 6-bit AD converter, and 43-ps/5.2-GHz macrocell array LSIs-have been developed. Concerning future performance, a cutoff frequency of more than 50 GHz for a scaled-down transistor is expected.<>
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