Validation Challenges in Recent Trends of Power Management in Microprocessors

Modern PC power management has evolved to provide Always On, Always Connected, and Instant Resume kind of experiences to the user, along with longer battery life. It enhances productivity and greatly improves the user experience and brings in a Mobile-like experience to the PC user. The connectivity to the system is maintained even during the standby, which keeps the data up-to-date and readily available, when the user resumes the system from standby. This modern behavior needs to be supported at both the Operating System and at the SoC level. On Windows, this is supported through the ‘Modern Standby’ feature followed by the ‘Active Idle’ feature supported by the SoC.Legacy Standby (S3) validation involved mostly checking the power, software and hardware status and the corresponding wake capabilities. Validating Modern Standby involves a lot of new methodologies and techniques such as Sleep Residency during standby, seamless transition between various Power Management states (avoiding system crashes and hangs), Instant Resume time and seamless connectivity during Modern Standby.This paper discusses the new validation methodologies established to accelerate the failure detection during these complex and error-prone use cases, and defines effective debug methodologies, thus enabling early fixing of these issues. The new validation methodologies include residency measurement techniques, verifying system stability during state transitions and measuring resume time from standby.