T. Agarwal, O. Badami, S. Ganguly, S. Mahapatra, D. Saha
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引用次数: 7
摘要
本文研究了栅极全能(GAA)垂直纳米线晶体管(VNWFET)作为未来非易失性存储器(NVM)如电阻随机存取存储器(RRAM)、相变随机存取存储器(PCRAM)和自旋转矩传输存储器(STT-RAM或MRAM)中的存取元件的应用。我们主要选择直流(DC)参数ION和ION/IOFF作为我们的优值(FOM),并通过考虑各种关键工艺参数(如沟道长度、鳍片掺杂、栅极重叠和纳米线晶体管的横截面形状)来优化垂直纳米线场效应管。此外,使用优化后的器件在3×3交叉棒阵列中,我们评估了由于有源器件对相邻非活动器件的读/写干扰。我们发现,优化后的存取器件可用于不同存储器件所需的电流额定值范围,离子最高可达0.19 a /μm2, IOFF低至2 nA/μm2。
Design optimization of gate-all-around vertical nanowire transistors for future memory applications
This paper investigates the application of gate-all-around (GAA) vertical nanowire transistors (VNWFET) as an access element in future non-volatile memories (NVM) such as resistive random-access memory (RRAM), phase-change random access memory (PCRAM) and spin-torque-transfer memory (STT-RAM or MRAM). We primarily choose direct-current (DC) parameters ION and ION/IOFF as our figure of merit (FOM) and optimize the vertical nanowire FET by taking various critical process parameters into account such as channel length, fin doping, gate overlap, and cross-sectional shape of the nanowire transistor. Further, using the optimized device in a 3×3 cross-bar array arrangement, we evaluate the read/write disturb due to the active device on it's neighboring inactive devices. We show that the optimized access device can be used for a range of currents ratings required by different memory devices, ION being as high as 0.19 A/μm2 and IOFF being as low as 2 nA/μm2.