C. O. Chui, Hyoungsub Kim, P. McIntyre, K. Saraswat
{"title":"一种集成金属栅极和改进的高/声压kappa/介电体的锗NMOSFET工艺","authors":"C. O. Chui, Hyoungsub Kim, P. McIntyre, K. Saraswat","doi":"10.1109/IEDM.2003.1269316","DOIUrl":null,"url":null,"abstract":"A simple and novel self-aligned gate-last MOS process integrating metal gates and high-k dielectrics on Ge has been demonstrated. Improved surface passivation for excellent gate dielectric and field isolation, and n-type dopant incorporation with high surface concentration and shallow junctions has been developed. Conventional VLSI type Ge n-MOSFETs have been fabricated.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"49","resultStr":"{\"title\":\"A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/ dielectrics\",\"authors\":\"C. O. Chui, Hyoungsub Kim, P. McIntyre, K. Saraswat\",\"doi\":\"10.1109/IEDM.2003.1269316\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simple and novel self-aligned gate-last MOS process integrating metal gates and high-k dielectrics on Ge has been demonstrated. Improved surface passivation for excellent gate dielectric and field isolation, and n-type dopant incorporation with high surface concentration and shallow junctions has been developed. Conventional VLSI type Ge n-MOSFETs have been fabricated.\",\"PeriodicalId\":344286,\"journal\":{\"name\":\"IEEE International Electron Devices Meeting 2003\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"49\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Electron Devices Meeting 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2003.1269316\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269316","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/ dielectrics
A simple and novel self-aligned gate-last MOS process integrating metal gates and high-k dielectrics on Ge has been demonstrated. Improved surface passivation for excellent gate dielectric and field isolation, and n-type dopant incorporation with high surface concentration and shallow junctions has been developed. Conventional VLSI type Ge n-MOSFETs have been fabricated.