90纳米CMOS工艺的中子软错误率测量和SRAM从0.25-/spl mu/m到90纳米一代的缩放趋势

IEEE International Electron Devices Meeting 2003 Pub Date : 2003-12-08 DOI:10.1109/IEDM.2003.1269336

P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, S. Borkar

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引用次数: 172

摘要

采用最先进的90纳米CMOS技术测量了中子软错误率(SER)与电压和面积的关系。由于电压降低10%，SER增加了18%，并且与二极管面积成线性比例。在0.25 /spl mu/m、0.18 /spl mu/m、0.13 /spl mu/m和90 nm的sram中，每代SER提高了8%。

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Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.

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IEEE International Electron Devices Meeting 2003

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