{"title":"1T1R忆阻存储器的故障建模与测试","authors":"Yong-Xiao Chen, Jin-Fu Li","doi":"10.1109/VTS.2015.7116247","DOIUrl":null,"url":null,"abstract":"Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"53","resultStr":"{\"title\":\"Fault modeling and testing of 1T1R memristor memories\",\"authors\":\"Yong-Xiao Chen, Jin-Fu Li\",\"doi\":\"10.1109/VTS.2015.7116247\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.\",\"PeriodicalId\":187545,\"journal\":{\"name\":\"2015 IEEE 33rd VLSI Test Symposium (VTS)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"53\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 33rd VLSI Test Symposium (VTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2015.7116247\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 33rd VLSI Test Symposium (VTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2015.7116247","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fault modeling and testing of 1T1R memristor memories
Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.