延迟插入法在电热电路分析中的应用

D. Klokotov, J. Schutt-Ainé, W. Beyene, D. Mullen, Ming Li, R. Schmitt, Ling Yang
{"title":"延迟插入法在电热电路分析中的应用","authors":"D. Klokotov, J. Schutt-Ainé, W. Beyene, D. Mullen, Ming Li, R. Schmitt, Ling Yang","doi":"10.1109/EPEPS.2011.6100242","DOIUrl":null,"url":null,"abstract":"In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.","PeriodicalId":313560,"journal":{"name":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Application of the latency insertion method to electro-thermal circuit analysis\",\"authors\":\"D. Klokotov, J. Schutt-Ainé, W. Beyene, D. Mullen, Ming Li, R. Schmitt, Ling Yang\",\"doi\":\"10.1109/EPEPS.2011.6100242\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.\",\"PeriodicalId\":313560,\"journal\":{\"name\":\"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPS.2011.6100242\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPS.2011.6100242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

本文提出了一种基于延迟插入法(LIM)的快速电路仿真技术,用于电路和高性能系统的电热分析。将该方法应用于片上和片外三维互连网络的建模。结果表明,该方法能够模拟高速高性能VLSI电路在预布局设计阶段发生的电和热现象。
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Application of the latency insertion method to electro-thermal circuit analysis
In this paper, a fast circuit simulation technique based on the Latency Insertion Method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. The method is applied to the modeling of on-chip and off-chip 3D-interconnect networks. The proposed method is shown to be capable of modeling both electrical and thermal phenomena occurring in high speed, high performance VLSI circuits at the pre-layout design stages.
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