{"title":"k波段快跳频合成器的设计","authors":"Zhicheng Hu, Guolin Sun","doi":"10.1109/ICAM.2017.8242155","DOIUrl":null,"url":null,"abstract":"The design and implementation of a K-band fast hopping frequency synthesizer based on DDS and PLL is described. Main technical specifications are as follows: frequency ranges from 24GHz to 27GHz, step frequency is 50MHz and lock time is less than 150ns. The parameters of loop filter and the analyses of phase noise and lock time are provided by MATLAB simulation to verify the feasibility of the design. Final test results of the circuits proves that the targets of performance are achieved.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a K-band fast hopping frequency synthesizer\",\"authors\":\"Zhicheng Hu, Guolin Sun\",\"doi\":\"10.1109/ICAM.2017.8242155\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design and implementation of a K-band fast hopping frequency synthesizer based on DDS and PLL is described. Main technical specifications are as follows: frequency ranges from 24GHz to 27GHz, step frequency is 50MHz and lock time is less than 150ns. The parameters of loop filter and the analyses of phase noise and lock time are provided by MATLAB simulation to verify the feasibility of the design. Final test results of the circuits proves that the targets of performance are achieved.\",\"PeriodicalId\":117801,\"journal\":{\"name\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAM.2017.8242155\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242155","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a K-band fast hopping frequency synthesizer
The design and implementation of a K-band fast hopping frequency synthesizer based on DDS and PLL is described. Main technical specifications are as follows: frequency ranges from 24GHz to 27GHz, step frequency is 50MHz and lock time is less than 150ns. The parameters of loop filter and the analyses of phase noise and lock time are provided by MATLAB simulation to verify the feasibility of the design. Final test results of the circuits proves that the targets of performance are achieved.
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