{"title":"断言检查器——质量设计的推动者","authors":"M. Boule, Z. Zilic","doi":"10.1109/MNRC.2008.4683387","DOIUrl":null,"url":null,"abstract":"This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current state of the MBAC tool, compared to the best known checker generator from IBM.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Assertion checkers - enablers of quality design\",\"authors\":\"M. Boule, Z. Zilic\",\"doi\":\"10.1109/MNRC.2008.4683387\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current state of the MBAC tool, compared to the best known checker generator from IBM.\",\"PeriodicalId\":247684,\"journal\":{\"name\":\"2008 1st Microsystems and Nanoelectronics Research Conference\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 1st Microsystems and Nanoelectronics Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MNRC.2008.4683387\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 1st Microsystems and Nanoelectronics Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MNRC.2008.4683387","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current state of the MBAC tool, compared to the best known checker generator from IBM.
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