一种高效的二维管道结构，用于数字信号处理操作

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186137

P. Mukherjee

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摘要

讨论了一种有效的二维流水线收缩结构，它可以在2n+b/2时间单位内完成卷积运算，而不是在单处理器上顺序算法需要O(bn)时间。本文还简要讨论了一种非常高效的流水线乘法器，它具有收缩方案的所有优点，并且可以作为中等规模集成(MSI)单元的ASIC库的一部分。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An efficient two-dimensional pipeline architecture for digital signal processing operation

An efficient two-dimensional pipelined systolic architecture which can perform convolution operations in 2n+b/2 time units as opposed to O(bn) time needed for the sequential algorithm on a single processor is discussed. A very efficient pipelined multiplier, which enjoys all the merits of a systolic scheme and can be made a part of an ASIC library of medium-scale integration (MSI) cells, is also briefly discussed.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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