掺杂偏析的纳米线与平面UTB SOI肖特基势垒mosfet

2012 13th International Conference on Ultimate Integration on Silicon (ULIS) Pub Date : 2012-03-06 DOI:10.1109/ULIS.2012.6193353

L. Knoll, A. Schafer, S. Trellenkamp, K. Bourdelle, Q. Zhao, S. Mantl

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引用次数: 6

摘要

肖特基势垒mosfet是在超薄体(UTB) SOI上制作的，具有平面和nw阵列的器件几何形状。采用注入硅化物(IIS)来降低n型和p型mosfet的肖特基势垒高度。NW阵列的栅极控制增强了n型mosfet的漏极诱导势垒降低(DIBL)和亚阈值斜率，而校正电流下降。在p型mosfet上的电流和离子/开关比得到提高。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Nanowire and planar UTB SOI Schottky Barrier MOSFETs with dopant segregation

Schottky Barrier MOSFETs were fabricated on ultra thin body (UTB) SOI with planar and NW-array device geometry. Implantation into Silicide (IIS) was used to lower the Schottky Barrier height for n- and p-type MOSFETs. The enhanced gate control of the NW array reduces Drain Induced Barrier Lowering (DIBL) and improves the subthreshold slope in n-type MOSFETs, whereas the corrected current drops. In p-type MOSFETs on current and Ion/Ioff ratio is enhanced.

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2012 13th International Conference on Ultimate Integration on Silicon (ULIS)

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