面向并行运算的FPGA结构的栅极密度优势

Takumi Fujimori, Minora Watanabe
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引用次数: 1

摘要

最近,除了对图形处理单元(gpgpu)、Xeon Phi等通用计算的研究外,还报道了许多对现场可编程门阵列(FPGA)硬件加速器的研究。由于并行处理对于FPGA上的加速应用是必不可少的,因此实现大量并行处理电路对于提高FPGA硬件加速器的性能非常重要。在为传统FPGA实现并行操作时,会产生一些浪费:相同的上下文存储在配置内存的许多区域中。这种浪费提出了一个关键问题,因为在大多数情况下,用作加速器的fpga只执行并行处理。因此,本文提出了一种利用通用配置上下文的面向并行操作的FPGA。在此,我们描述了门密度、传播延迟和编译时间在面向并行操作的fpga中的优势。
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Gate density advantage of parallel-operation-oriented FPGA architecture
Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.
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